Linux VFIO series adds CXL Type-2 accelerator passthrough
NVIDIA’s Manish Honap posts work that lets guests drive a virtual HDM decoder and device reset while the host keeps the physical mapping.
Manish Honap of NVIDIA has posted a revised Linux kernel series that adds VFIO passthrough for CXL Type-2 accelerators. The design lets a guest run its own virtual Host-managed Device Memory (HDM) decoder and reset the device, while the host alone owns the physical decoder and the host physical address where the coherent memory lands. The guest only chooses a guest physical address.
That split matters because Type-2 devices expose coherent CXL.mem alongside compute. Without host control of the physical decode, passthrough would either break isolation or leave the guest unable to use the memory window the hardware expects. The first cut is narrow: a single, non-interleaved, firmware-committed endpoint decoder. Devices with multiple decoders, interleaving, or a reset the host cannot service are rejected. Admins and variant drivers can also turn the CXL extensions off and bind the device as plain vfio-pci.
On open, the provider joins the device to the CXL topology, exposes the HDM range as an mmap-able vendor region, and offers a second, read-only region that serves live decoder registers. Direct guest and host access to the physical decoder block through the BAR is blocked so a stray read cannot escalate into a fatal host error. The HDM range has no struct pages, so memory errors on it are registered for containment: unmap and SIGBUS to the holder rather than a host SError. For IOMMU stage-2 setup, the same range is exportable as a dma-buf so iommufd can map the coherent window the device’s ATS DMA targets.
Function reset is routed through the CXL DVSEC sequence instead of FLR, which would clear coherent state and corrupt the decoder. Secondary bus reset handling clears the HDM access gate when the upstream port actually delivers the reset, and a later CXL reset restores the decoder. A device-info flag and a small region capability tell the VMM it has a Type-2 assignment and where to place the trapped decoder window. Driver-API documentation records the address model, regions, reset contract, and kernel versus VMM split.
The series builds on CXL reset work already staged for the kernel and keeps register emulation in an on-demand vfio-cxl provider loaded by vfio-pci-core, rather than a separate variant driver.