RISC-V IOMMU gains MSI remapping, unlocking DMA and VFIO

Andrew Jones of Qualcomm has posted a kernel series that adds MSI remapping to the RISC-V IOMMU, the missing piece that lets the architecture turn on the standard IOMMU DMA path and VFIO-based device assignment by default.

Until now, a device’s DMA could be translated through the IOMMU while its MSI writes still targeted raw physical addresses in the IMSIC interrupt controller. That mismatch blocked the usual IOMMU_DMA plumbing and kept paging domains off by default. The series fixes the gap by pre-mapping every IMSIC page into a domain-wide PA-to-IOVA table at IRQ allocation time, then rewriting composed MSI messages with an O(1) lookup so affinity changes (which run in atomic context and alter the MSI address itself) still hit the right translated target.

The design follows the ARM approach in spirit but diverges where IMSIC requires it: ARM’s doorbell address is fixed per ITS instance, so one cached IOVA lasts for the descriptor’s life; IMSIC has no such fixed target, so the table must cover every possible host page up front.

With the DMA path in place, the same series wires the remaining pieces for PCIe assignment. The RISC-V IOMMU now reports DMA cache-coherency, VFIO type1 and KVM_VFIO are enabled for the architecture, defconfig builds IOMMUFD and VFIO as modules with cdev support, and the generic VFIO/iommufd selftests can be built for RISC-V. Tomasz Jeznach contributed several of the enablement patches.

Two limits remain. The interrupt-remapping domain does not yet validate MSI data, so VFIO still needs allow_unsafe_interrupts=1, and direct MSI routing to guest interrupt files (irqbypass) is deferred to a follow-up series. Even so, the change moves RISC-V from IOMMU DMA as a special case to the same default model used on arm64, x86, and s390, and makes hardware device assignment a realistic option for RISC-V KVM guests.